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DATA SHEET
O K I A S I C P R O D U C T S
MSM13Q/14Q000 0.35 m Sea of Gates Arrays
November 1999
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Oki Semiconductor
MSM13Q0000/14Q0000
0.35 m Sea of Gates Arrays DESCRIPTION
Oki's 0.3 5 m ASIC products deliver ultra-high performance and high density at low power dissipation. The MSM13Q0000/14Q0000 series devices (referred to as "MSM13Q/14Q") are implemented with the industry-standard Cell-Based Array (CBA) architecture in a Sea-of-Gates (SOG) structure. Built in a 0.35 m drawn CMOS technology (with an L-Effective of 0.27 m), these SOG devices are available in three layers (MSM13Q) and four layers (MSM14Q) of metal. The semiconductor process is adapted from Oki's production-proven 64-Mbit DRAM manufacturing process. The MSM13Q/14Q Series contains 6 arrays each, offering over 1 million raw gates and 352 I/O pads. Up to 66% and 90% of the raw gates can be used for the 3-layer and 4-layer arrays, respectively. Oki's 0.35 m family is optimized for 3-V core operation with optimized 3-V I/O buffers and 5-V tolerant 3-V buffers. These SOG products are designed to fit the most popular plastic quad flat packs (QFPs), thin QFPs (TQFPs) , and plastic ball grid array (PBGA) packages. The MSM13Q/14Q Series uses the popular CBA architecture from Silicon Architects of Synopsys which mixes two types of cells (8-transistor compute cells and 4-transistor drive cells) on the same die to deliver high gate density and high drives. The CBA is supported by a rich macro library, optimized for synthesis. Memory blocks are efficiently created by Oki's memory compilers to generate single- and dual-port RAM's in high-density and low-power configurations with synchronous RAM options. As such, the MSM13Q/14Q series is well suited to memory-intensive designs with high production volumes approaching the real estate and cost savings of standard cells. At the same time, its SOG architecture allows rapid prototyping turnaround times. Thus, Oki's MSM13Q/14Q family offers the best of two worlds: quick prototyping of a gate array and low production cost of a standard cell. Oki's 0.35 m ASIC products are supported by leading-edge CAD tools including a synthesis-linked floorplanner, motive static timing analyzer, and H-clock tree methodology. They are further supported by specialized macrocells including phase-locked loop (PLL), pseudo-emitter coupled logic (PECL), peripheral component interconnect (PCI), universal synchronous receiver/transmitter (UART) cells, and ARM7TDMI RISC cores.
FEATURES
* 0.35 m drawn 3- and 4-layer metal CMOS * Optimized 3.3-V core * Optimized 3-V I/O and 3-V I/O that is 5-V tolerant * CBA SOG architecture * Over 1.0M raw gates and 352 pads * User-configurable I/O with VSS, VDD, TTL, 3state, and 1- to 24-mA options * Slew-rate-controlled outputs for low-radiated noise * H-clock tree cells which reduce the maximum skew for clock signals * User-configurable single and dual-port; synchronous or asynchronous memories * Specialized macrocells including PLL, PECL, PCI, UART, and ARM7TDMI * Floorplanning for front-end simulation, backend layout controls, and link to synthesis * Joint Test Action Group (JTAG) boundary scan and scan-path ATPG * Support for popular CAE systems, including Cadence, IKOS, Mentor Graphics, Synopsys, Viewlogic, and Zycad
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MSM13Q/14Q FAMILY LISTING
MSM13Q/14Q Series 0150 0230 0340 0530 0840 1020 PAD No. 144 176 208 256 320 352 Raw Gate (Gates) 157,192 242,400 346,176 536,400 847,048 1,033,000 Usable Gate M13Q(3LM) 105,319 152,712 204,244 289,656 415,054 475,180 Usable Gate M14Q(4LM) 143,045 208,464 276,941 391,572 567,522 650,790 Raw Gate Row 196 240 288 360 452 500 Column 802 1,010 1,202 1,490 1,874 2,066
ARRAY ARCHITECTURE
The primary components of a 0.35 m MSM13Q/14Q circuit include: * * * * * * * I/O base cells Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base modules containing three compute cells for each drive cell Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with 4 pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO). The array architecture uses optimally sized transistors to efficiently implement logic and memory in a metal programmable technology. CBA uses two types of cells: compute cells and drive cells. The compute cell employs four PMOS and four NMOS trasnsistors whose sizes are optimized for logic and memory implementations as shown in Figure 1. The quantity and size of the transistors in a compute cell are carefully selected to maximize the efficiency of most commonly used functions in VLSI design. The drive cell consists of two large PMOS pull-up transistors and two large pull-down transistors. The compute and drive cells are tiled to create a channelless core array, with three comput cells for each drive cell as shown in Figure 2. The 3:1 ratio of compute to drive cells was selected for optimal implementation of emerging applications. Macrocells are created using either compute cells, drive cells, or combinations of compute and drive cells.
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Compute Cell
Compute Cell
Compute Cell
Drive Cell
Figure 1. Base Cell Consisting of Three Compute Cells and One Drive Cell
Compute Cell
Drive Cell
Figure 2. Core Array with Base Cell Mirrored Horizontally and Vertically
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (VSS = 0 V, Tj = 25C) [1]
Parameter Power supply voltage Input voltage Normal buffers 5-V tolerant Output voltage Normal buffers 5-V tolerant Input current Normal buffers 5-V tolerant Output current per I/O Normal buffers 5-V tolerant Storage temperature Symbol VDD VI VI VO VO II II IO IO Tstg IO = 1, 2, 4, 6, 8, 12, 24 mA IO = 2, 4, 6, 8, 12 mA - Conditions Rated Value -0.3 to +4.6 -0.3 to VDD+0.3 -0.3 to 6.0 -0.3 to VDD+0.3 -0.3 to 6.0 -10 to +10 -6 to +6 -24 to +24 -8 to +8 -65 to +150 Unit V V
V
mA
mA C
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (VSS = 0 V)
Parameter Power supply voltage Junction temperature Symbol VDD (3 V) Tj Rated Value +3.0 to +3.6 -40 to +85 Unit V C
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DC Characteristics (VDD = 3.0 to 3.6 V, VSS = 0 V, Tj = -40C to +85C)
Rated Value Parameter High-level input voltage Normal buffer 5-V tolerant Low-level input voltage Normal buffer 5-V tolerant TTL- level Schmitt trigger input threshold voltage Normal buffer Symbol VIH VIH VIL VIL Vt+ VtVt 5-V tolerant Vt+ VtVt High-level output voltage Normal buffer VOH TTL input TTL input TTL input Vt+ - VtTTL 5-V tolerant input Vt+ - VtIOH = -100 A IOH = -1, -2, -4, -6, -8, -12, -24 mA 5-V tolerant VOH IOH = -100 A IOH = -1, -2, -4, -6, -8, -12 mA Low-level output voltage Normal buffer VOL IOL = 100 A IOL = 1, 2, 4, 6, 8, 12, 24mA 5-V tolerant VOL IOL = 100 A IOL = 1, 2, 4, 6, 8, 12 mA High-level input current Normal buffer IIH VIH = VDD VIH = VDD (50-k pull-down) 5-V tolerant IIH VIH = VDD VIH = VDD (50-k pull-down) Low-level input current Normal buffer IIL VIL = VSS VIL = VSS (50-k pull-up) VIL = VSS (3-k pull-up) 5-V tolerant 3-state output leakage current Normal buffer IIL IOZH VIL = VSS VOH = VDD VOH = VDD (50-k pull-down) IOZL VOL = VSS VOL = VSS (50-k pull-up) VOL = VSS (3-k pull-up) 5-V tolerant IOZH VOH = VDD VOH = VDD (50-k pull-down) IOZL Stand-by current
[3] [1]
Conditions
Min. 2.0 2.0 -0.3 -0.3 - 0.7 0.4 - 0.7 0.4 VDD - 0.2 2.4 VDD - 0.2 2.4 - - - - - 10 - 10 -10 -200 -3.3 -10 - 10 -10 -200 -3.3 - 10 -10
Typ - - - -
[2]
Max. VDD + 0.3 5.5 0.8 0.8 2.0 - - 2.0 - - - - - - 0.2 0.4 0.2 0.4 10 200 10 200 -10 -0.3 - 10 200 - -10 -0.3 10 200 -
Unit
1.5 1.0 0.5 1.5 1.0 0.5 - - - - - - - - 0.1 66 0.1 66 -0.1 -66 -1.1 -0.1 0.1 -66 -0.1 -66 -1.1 0.1 66 -0.1 Design Dependent
V
A
mA A
A
mA A
VOL = VSS Output open, VIH = VDD, VIL = VSS
IDDQ
A
1. JEDEC Compatible; JESD8-1A LVTTL. 2. Typical condition is VDD = 3.3 V and Tj = 25oC on a typical process. 3. RAM/ROM should be in powerdown mode.
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AC Characteristics (VDD = 3.3 V, VSS = 0 V, Tj = 25C)
Parameter Internal gate propagation delay Inverter Driving Type 1X 2X 4X 2-input NAND 1X 2X 2-input NOR 1X 2X Inverter 1X 2X 4X 2-input NAND 1X 2X 2-input NOR 1X 2X Toggle frequency Input buffer propagation delay Output buffer propagation delay TTL level normal input buffer TTL level 5-V tolerant buffer Push-pull Normal output buffer 3-state 5-V tolerant buffer Output buffer transition times [4] Push-pull Normal output buffer 3-state 5-V tolerant buffer
1. 2. 3. 4.
Conditions [1] [2] F/O = 2, L = 0 mm VDD = 3.3 V
Rated Value [3] 0.082 0.068 0.062 0.14 0.13 0.16 0.14
Unit
ns
F/O = 2, L = 1 mm VDD = 3.3 V
0.19 0.13 0.097 0.28 0.20 0.34 0.24
F/O= 1, L = 0 mm F/O = 2,L = 1 mm
1040 0.35 0.64
MHz
4 mA 8 mA 12 mA 4 mA
CL = 20pF CL= 50 pF CL = 100 pF CL = 20 pF
2.15 2.25 2.82 2.41 ns
12 mA
CL = 100 pF
4.68 (r) 3.48 (f) 3.53 (r) 3.24 (f)
4 mA
CL = 20 pF
Input transition time in 0.2 ns / 3.3 V. Typical condition is VDD = 3.3 V and Tj = 25oC. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process. Output rising and falling times are both specified over a 10 to 90% range.
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MACRO LIBRARY
Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following figure illustrates the main classes of macrocells and macrofunctions available.
Examples Basic Macrocells NANDs NORs EXORs Latches Flip-Flops Combinational Logic
Basic Macrocells with Scan test
Flip-Flops
Clock Tree Driver Macrocells Macrocells 3V, 5V Tolerant Output Macrocells 3-State Outputs Push-Pull Outputs PECL Outputs Counters Shift Registers Open Drain Outputs Slew Rate Control Outputs PCI Outputs
MSI Macrocells
Mega/Special Macrocells [1] Macro Library
UART PLL
USB Controller Ethernet Controller
3-V, 5-V Tolerant Input Macrocells
Inputs Inputs with Pull-Downs Inputs with Pull-Ups PECL Inputs
3-V, 5-V Tolerant Bi-Directional Macrocells Oscillator Macrocells
I/O PCI I/O
I/O with Pull-Downs I/O with Pull-Ups
Gated Oscillators
Memory Macrocells
CBA RAMs: Single-Port RAMs (asynchronous or synchronous) Dual-Port RAMs (asynchronous)
Macrofunctions
MSI Macrofunctions
[1] Under development
4-Bit Register/Latches
Figure 3. Oki Macrocell and Macrofunction Library
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Macrocells for Driving Clock Trees Oki offers H-clock-tree drivers that minimize clock skew. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the H-clock-tree driver-macrocells include: * * * * * * * True RC back annotation of the clock network Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Automatic branch length minimization Dynamic driver placement Allows multiple clock trees
Clock
Figure 4. H-Clock-Tree Structure
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OKI ADVANCED DESIGN CENTER CAD TOOLS
Oki's advanced design center CAD tools include support for the following: * * * * Floorplanning for front-end simulation, back-end layout control, and link to synthesis Clock tree structures improve first-time silicon success by eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions to accurately model package requirements (in development)
Table 1: CAD Design Tools
Vendor Cadence Platform HP9000, 7xx IBM RS6000 Sun(R) [2] Operating System [1] HP-UX AIX SunOS, Solaris Vendor Software/Revision [1] ComposerTM VerilogTM VeritimeTM VerifaultTM SynergyTM ConceptTM [3] LeapfrogTM NSIM Gemini/Voyager IDEATM QuickVHDL QuickSim IITM QuickPathTM QuickFaultTM QuickGradeTM AutoLogicTM DFT Advisor Design CompilerTM HDL/VHDL CompilerTM Test CompilerTM VSSTM V-System Description Design capture Simulation Timing analysis Fault grading Design synthesis Design capture VHDL simulation Simulation Design capture VHDL simulation Logic simulation Timing analysis Fault grading Fault grading Design synthesis Test synthesis Compilation Design synthesis Test synthesis VHDL simulation VHDL Simulation
IKOS Mentor GraphicsTM
HP9000, 7xx, Sun [2] HP9000, 7xx Sun [2]
HP-UX, SunOS, Solaris HP-UX SunOS, Solaris
Synopsys (Interface to Mentor Graphics, VIEWLogic) Model Technology, Inc. (MTI)
IBM RS6000 HP9000, 7xx Sun [2] HP9000, 7xx Sun [2] PC
AIX HP-UX SunOS, Solaris HP-UX SunOS, Solaris. Win95/NTTM
VIEWLogic
PC Sun [2]
WindowsTM, Windows NTTM SunOS, Solaris
Workview OfficeTM PowerviewTM Vantage Optium Motive ViewSimTM with VSO
Design capture Simulation VHDL simulation Timing analysis Design synthesis Simulation
1. Contact Oki Application Engineering for current software versions. 2. Sun or Sun-compatible. 3. Sun and HP platform only.
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Design Process The following figure illustrates the overall IC design process and shows the three main interface points between external design houses and Oki ASIC Application Engineering.
Level 1 [5] Schematics VHDL/HDL Description Synthesis LSF[2] CDC [1] Floorplanning Floorplanning Gate-Level Simulation Test Vectors
CAE Front-End
Level 2 Netlist Conversion (EDIF 200) Scan Insertion (Optional) CDC [1] Floorplanning Pre-Layout Simulation (Cadence Verilog) Test Vector Conversion (Oki TPL [4]) TDC [3]
Level 2.5 [5] Layout Fault Simulation [6] ( Zycad) Oki Interface Automatic Test Pattern Generation (Synopsys Test Compiler)
Verification (Cadence DRACULA)
Post-Layout Simulation (Cadence Verilog)
Level 3 [5] Manufacturing Prototype Test Program Conversion
[1] [2] [3] [4] [5] [6]
Oki's Circuit Data Check (CDC) program verifies logic design rules. Oki's Link to Synthesis Floorplanning (LSF) toolset transfers post-floorplanning timing for resynthesis. Oki's Test Data Check (TDC) program verifies test vector rules. Oki's Test Pattern Language (TPL). Alternate Customer-Oki design interfaces available in addition to standard level 2. Standard design process includes fault simulation.
Figure 5. Oki's Design Process
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Automatic Test Pattern Generation Oki's 0.35 m ASIC technologies support Automatic Test Pattern Generation (ATPG) using full scanpath design techniques, including the following: * * * * * * * * * Increases fault coverage 95% Uses Synopsys Test Compiler Inserts scan structures automatically Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction
ATPG methodology is described in detail in Oki's 0.35 m Scan Path Application Note.
Combinational Logic A FD1AS D C SD SS Q B FD1AS D C SD SS Q Scan Data Out
Scan Data In
QN
QN
Scan Select
Figure 6. Full Scan Path Configuration
Floorplanning Design Flow Oki offers three floorplanning tools for high-density ASIC design. The two main purposes for Oki's floorplanning tool are to: * Ensure conformance of critical circuit performance specifications * Shorten overall design turnaround time (TAT) The supported floorplanners are: Cadence DP3, Gambit GFP, and Oki's internal floorplanner. In a traditional design approach with synthesis tools, timing violations after prelayout simulation are fixed by manual editing of the netlist. This process is difficult and time consuming. Also, there is no physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using predicted interconnection delay due to wire length. Therefore, synthesis tools may create over-optimized results. To minimize these problems, Synopsys proposed a methodology called Links to Layout (LTL). Based on this methodology, Oki developed an interface between Oki's floorplanners and the Synopsys environment, called Link Synopsys to Floorplanner (LSF). Because not all Synopsys users have access to the Synopsys Floorplan Management tool, Oki developed the LSF system to support both users who can access
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Synopsys Floorplan Management and users who do not have access to Synopsys Floorplan Management. More information on OKI's floorplanning capabilities is available in Oki's Application Note, Using Oki's Floorplanner: Standalone Operation and Links to Synopsys.
Incremental Optimization with Physical Information Initial Synthesis HDL Entry No Constraints Met? Yes Invoke Import on Floorplanner Constraints Met? Gate Level Netlist (EDIF) Yes Initial Floorplan No Incremental Floorplan PDEF (Synopsis)
Constraints
Synthesis
Gate Level Netlist (EDIF)
Oki RC PDEF (Synopsys) Wire Load Model (Synopsys) Net Capacitance (Synopsys Script (Synopsys)
Invoke Export on Floorplanner Invoke Delay
Delay (SDF)
Load Back-Annotation Files
Constraints Met? = In Synopsys DC/DA = In Floorplanner Yes To Simulation and P&R
No Timing Optimization
Figure 7. LSF System Design Flow
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IEEE JTAG Boundary Scan Support Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into a design include: * * * * * * Improved chip-level and board-level testing and failure diagnostic capabilities Support for testing of components with limited probe access Easy-to-maintain testability and system self-test capability with on-board software Capability to fully isolate and test components on the scan path Built-in test logic that can be activated and monitored An optional Boundary Scan Identification (ID) Register
Oki's boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Either the customer or Oki can perform boundary-scan insertion. More information is available in Oki's JTAG Boundary Scan Application Note. (Contact the Oki Application Engineering Department for interface options.)
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PACKAGE OPTIONS
TQFP & LQFP Package Menu
Base Array MSM... 13Q/14Q0150 13Q/14Q0230 13Q/14Q0340 13Q/14Q0530 13Q/14Q0840 13Q/14Q1020 Body Size (mm) Lead Pitch (mm) TQFP I/O Pads 144 176 208 256 320 352 10 x 10 0.5 12 x 12 0.5 14 x 14 0.5
[1]
LQFP 100
q q q q q
64
q q q
80
q q q q
144
q q q q r r
176
208
q q r q q q q q q
20 x 20 0.5
24 x 24 0.5
28 x 28 0.5
1. I/O Pads can be used for input, output, bi-directional, power, or ground. q = Available now; r = In development
PQFP Package Menu
Base Array MSM... 13Q/14Q0150 13Q/14Q0230 13Q/14Q0340 13Q/14Q0530 13Q/14Q0840 13Q/14Q1020 Body Size (mm) Lead Pitch (mm) PQFP (42 Alloy) I/O Pads 144 176 208 256 320 352
[1]
PQFP (Cu-Alloy) 160 208 240
128
r r q q q r
r q q q q q q q r r
28 x 28 0.80
28 x 28 0.65
28 x 28 0.50
32 x 32 0.50
1. I/O Pads can be used for input, output, bi-directional, power, or ground. q = Available now; r = In development
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BGA Package Menu
Base Array MSM... 13Q/14Q0150 13Q/14Q0230 13Q/14Q0340 13Q/14Q0530 13Q/14Q0840 13Q/14Q1020 Body Size (mm) Ball Pitch (mm) 1. I/O Pads can be used for input, output, bi-directional, power, or ground. q = Available now; r = In development I/O Pads 144 176 208 256 320 352
q q q q q q q
[1]
256
352
27 x 27 1.27
35 x 35 1.27
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Notes:
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The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 1999 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki.
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